I. Field
The present invention relates generally to electronics, and more specifically to a cached memory system and a cache controller for an embedded digital signal processor (DSP).
II. Background
DSPs are specialized microprocessors that are specifically designed to execute mathematical computations very rapidly. DSPs are widely used in a variety of consumer electronic devices such as cellular phones, personal digital assistants (PDAs), and so on. For example, a cellular phone typically includes an application specific integrated circuit (ASIC) to perform signal processing for wireless communication, and this ASIC may contain an embedded microprocessor for general-purpose use and an embedded DSP to perform computation-intensive tasks.
Microprocessors and DSPs both use memory to hold instructions and data, so their performance is highly dependent on the characteristics of the memory system. As microprocessors and DSPs scale upward in clock speed to meet increasing processing demands, it is necessary to use a cached memory system so that (1) memory accesses do not become a bottleneck and (2) memory speed does not limit the processor clock speed. The cache memory system typically includes an external main memory and one or more cache memories. Cache memories are small, fast memories located on-chip and close to the processors in order to store instructions and data used by these processors. The fast cache memories improve processing speed because the processors can retrieve input data and store results faster. The main memory is a large, slower memory located off-chip and stores instructions and data for the cache memories.
The use of the cached memory system can cause several problems for the embedded DSP. First, reception of high-rate input data is complicated because of overhead needed to determine whether the data should be stored in the cache memories or the external memory. Second, it may be difficult to ensure completion of real-time processing tasks within specified time deadlines. This difficulty may result when the instructions and/or data needed by the DSP is not in the cache memories, in which case the DSP would need to wait for the instructions/data to be fetched from the external memory. These two problems are exacerbated when one or more other processors share the external memory with the DSP, and the DSP is not guaranteed instant access to the external memory.
There is therefore a need in the art for a cached memory system that can address the problems described above for an embedded DSP.